Many fiber optic links have been designed for transmission of synchronous or asynchronous data. However, very few designs have been developed which are efficient at operating in either mode and also operate over a wide range of data rates. Asynchronous links do not have the requirement for transmitting clock along with the data. The data may be of a type which does not require clock or the clock is embedded into the data by the host equipment and is inconsequential to the transmission equipment. Asynchronous links are typically simple in design and do not provide a capability for accepting and transmitting a clock containing relative timing information along with the data. The military designated AN/FAC-2B is a good example of an asynchronous fiber optic link. This link accepts a binary asynchronous input signal and produces the same signal at the output; of course, some distortion will occur due to noise and other factors.
Synchronous links have the requirement for accepting both data and clock input signals and generating both of these signals at the output. The positive and negative transitions of the clock signal indicate the beginning/ending and center of the data bit period. Thus, the clock signal may be used to sample the binary state of the data signal at the optimum time; i.e., center of the eye pattern. A common practice in the design of synchronous links is to embed clock into the transmitted bit stream by encoding the data. Commonly used codes are Manchester, Miller, and block codes. Link designs which use these codes are very effective, but generally require that the data rate for a specific link be constant. If the data rate is constant, the link design is greatly simplified. For example, clock is easily recovered using a phase-lock-loop circuit whose natural center frequency is selected to be twice the data rate. An obvious disadvantage of the phase-lock-loop circuit is the necessity for hardware changes to change data rate. Some applications require that synchronous data links have data rate transparency; i.e., they must operate over a range of data rates without hardware changes. "Bit synchronizers" which possess sufficient intelligence to adapt to the received data rate are one solution; however, clock acquisition time may be long, the equipment is expensive and historically has resulted in reduced reliability. An alternative solution is to transmit data and clock separately via two optical wavelength channels over a single fiber. The military designated AN/FAC 3 uses this approach. Problems with the wavelength division multiplex approach are component availability, loss associated with the multiplex and demultiplex couplers, and the high cost of the couplers and dual transmitters and receivers.
With regard to the receiver of the present invention, its design must take into consideration the characteristics of the optical system of the invention. Ideally, the carrier in such systems could be simply modulated in amplitude in response to the data. Unfortunately, there are serious trade-offs involved in the design of such systems.
The most fundamental of these trade-offs is between system simplicity and performance. If a sufficient amount of signal is available at the receiver of a link, a simple receiver may suffice. It is however, usually desirable that the system have as long a possible range between the transmitter and receiver as practical. Since the availability of optical emitters (LEDs and laser diodes) sets relatively well defined limits on the level of optical power that can be launched into the fiber, it is desirable to make the receiver as sensitive as possible. Furthermore, since the total amount of data that can be transferred over the link in any given amount of time is proportional to the data rate capacity of the system, it is also desirable that the receiver have a high bandwidth. One way of rating an optical link is thus a "performance factor" which is the product of the data rate and the maximum distance between the transmitter and receiver of the link.
The responsivity of PIN diode optical detectors is usually between 0.5 and 0.8 Amperes per watt of incident radiation. In order to achieve the highest possible data rate for the system, it is desirable to minimize the geometry of the detector (thus reducing capacitance), and the fiber (thus reducing dispersion). Unfortunately, reducing the diameter of the fiber limits the amount of light that can be launched into it. Furthermore, the geometry of the detector must be sufficient to capture all of the light available from the fiber.
The end result of such conflicting requirements is that the electronics of the receiver must work with extremely small, high frequency, optical signals if the system is to have the best possible data through-put. This fact in turn means that the electronic amplifiers of the receiver must be wide bandwidth, must exhibit very low levels of internally generated noise (especially in the first stages), and must be capable of working with extremely low input currents. Unfortunately, the bias currents in such wideband amplifiers are subject to long term drift due to thermal and aging effects. Since this drift is often many times larger than the desired detection level of the receiver, it is not practical to build an optical receiver that has a true DC (0 Hz) low end bandpass, and that at the same time exhibits a high performance factor.
In order to have a receiver exhibit an apparent DC (or very low frequency) low end bandpass frequency, many techniques have been used in the prior art. All such techniques change the format of the data in some way in order to accomplish this. Most of these schemes are based on two basic approaches: state encoding, and transition encoding.
In a state encoding system, the logical state of the data at the input of the transmitter is encoded and transmitted to the receiver. The receiver acts on such data by setting its data output to the decoded level (a logical 1 or 0). State encoding has the advantage that the link is kept busy with data, even when the input to the transmitter is in a constant state. This continuous activity makes timing synchronization (clock recovery) and automatic gain control (AGC) at the receiver relatively simple to accomplish.
The disadvantage of state encoding systems is that such systems are not totally data rate transparent. If the system clock is available to the encoder of the transmitter, and if it is in the frequency lock range of the receiver, these systems can transfer data with almost perfectly reproduced timing. For systems that do not have such clock information available, the transmitter must "over sample" the input data stream. Thus a jitter is introduced onto the data edges that is proportional in peak value to the sampling interval. The higher the ratio of optical transmission rate to data rate, the less the induced relative jitter, but the greater the wasted transmission bandwidth.
Because of these problems with state encoding, transition encoding has a great deal of appeal. In such a system, optical transmissions need only be made when a "transition event" occurs. Since transmissions are synchronized to these events, timing jitter is not induced into the data. As an additional advantage, the optical emitter is not made to dissipate as much power at low data rates. Thus power is conserved and the emitter reliability is increased.
The problem that has kept transition encoding from being used more widely is directly associated with the wide range of optical pulse densities. When the input to such a system is not changing rapidly, very little information is available to the receiver. This means that the receiver must be able to control its gain (AGC) in a smooth and predictable manner, with only sparse and irregular pulses of light to measure. Furthermore, the receiver must be able to track the extremes of such optical pulses in order to set a detection threshold at half way between the minimum and maximum amplitudes. These thresholds must thus be detected in extremely short intervals, but maintained for long periods. Additionally, it is necessary for these thresholds to track swiftly when more transition data is present. If these capabilities cannot be accomplished adequately, the receiver will exhibit cross coupling between data rate and sensitivity, or may be completely unstable under certain signal conditions.
In the prior art, AGC detection and clamping have usually been done with simple detection diodes that charge capacitors. In such circuits, a high impedance amplifier is then used to sense the voltage across the capacitor. The voltage stored in a capacitor is proportional to the charging current and the charge time (more properly it is proportional to the integral of the current over time.) Therefore, to maximize the hold time to charge time ratio, it has been necessary to minimize the charging impedance, and to maximize the discharging impedance in the circuit, thereby increasing the charging current and minimizing the discharging current. The use of very low forward resistance diodes (or active detectors) in the charge circuit, and very high impedance sense amplifiers in the discharge circuit can optimize such a circuit, but only within limits imposed by device characteristics.In the present invention time amplification or the stretching of pulses is used to solve this problem. This is possible because the charge in the capacitor is proportional to both current and time.
With regard to the clock symmetry restoration circuit of the present invention, prior art circuits for recovery of clock and data use either a ringing tank or a phase-locked loop.
The ringing tank approach uses a tuned circuit (tank) which is tuned to a frequency equal to (or an integral multiple of) the data rate. The tank is excited by the transitions of the incoming data, which are differentiated and applied as short pulses to the tank. The output of the tank is a sinusoidal waveform which decays slowly between data transitions. The sinusoidal waveform is converted to a square wave digital clock signal by a comparator (and frequency divider, if the tank is tuned to a multiple of the data rate). The clock signal is used to sample the incoming data in a D-type flip-flop.
The phase-locked loop (PLL) approach uses a voltage-controlled oscillator (VCO), phase detector, and loop filter to produce a clock signal locked to the data rate (or an integral multiple thereof). The phase detector samples the phase of the output signal from the VCO (or from a frequency divider circuit, if an integral multiple is used) at the times of the transitions of the incoming data. The phase information is filtered by the loop filter and fed to the VCO to control its frequency in a manner such that the phase of the output signal stays locked to the data transitions. The output clock signal from the VCO (or frequency divider) is used to sample the incoming data in a D-type flip-flop.
The aforementioned ringing tank and PLL approaches suffer from a limitation on the range of data rates they will tolerate for proper circuit operation.
The ringing tank must be rather precisely tuned to the data rate, or else phase error in the recovered clock will be excessive. The ringing tank is normally used only for fixed data rate transmission. If the ringing tank is to be applied to a range of data rates, some means for tuning and/or bandswitching must be provided. This requires either a manual adjustment which must be changed each time the data rate is changed, or a complex automatically adaptive tuning and bandswitching arrangement.
The PLL is automatically adaptive to data rate over a limited range, but has difficulty spanning many octaves without some additional means of tuning and/or bandswitching. If the range of data rate spans more than one octave, the possibility exists of improperly locking to undesired harmonics of the data rate. Additional circuitry is required to detect and correct for this condition. In addition, if many octaves are to be spanned, it is very difficult to build a VCO with the necessary combination of tuning range and frequency stability. The closed-loop response must also be a compromise design, less than optimum at most frequencies, because of the large variation in loop gain between the ends of the frequency range. Bandswitching approaches are also not attractive because they don't allow the clock recovery circuit to continuously track a signal which is smoothly changing in frequency from one band to another.